Predictor Virtualization: Teaching Old Caches New Tricks

From Anita Borg Institute Wiki

Ioana Burcea, University of Toronto

Abstract: We present Predictor Virtualization (PV), a technique that takes advantage of the existing memory hierarchy (i.e., processor caches and main memory) to emulate large prediction tables for hardware optimizations. PV increases the utility of traditional caches: in addition to being accelerators for slow off-chip memories, the on-chip memory hierarchy becomes leverage for effective predictor-based hardware optimizations.

GHC2010 Slides (pdf): Predictor Virtualization

Note: The animations are chopped compared to the original Keynote presentation. Please email me if you are interested in the Keynote presentation.

You can find the publications cited in this talk on my Research page.